Altera shifts to 40nm for Stratix 4

Altera has declared its hand in the race to build the densest field-programmable gate arrays (FPGAs) on the market, aiming to have parts made on TSMC’s 40/45nm process next year. Xilinx, which is the market leader, has yet to disclose its plans for follow-on products to the current Virtex-5 family, which is based on 65nm processes from two different foundries.

Altera will use TSMC’s G version of the 40nm process to build the Stratix 4 FPGAs, as well as two ASIC conversion families, designed to provide cheaper alternatives to the Stratix 3 and 4 FPGAs where customers are able to lock down their circuit designs.

Paul Hollingworth, senior director of the HardCopy product group at Altera, said: “The largest FPGA shipping today has 340,000 logic elements on it. We are doubling that.”

The largest part will not have serial transceivers on it, Hollingworth said. “The biggest part we can make is on the biggest [piece of] silicon that we can make.” Adding transceivers reduces the total programmable logic count to 530,000 on the 40nm process.

The company opted to use the TSMC 40G rather than the LP low-power process for the FPGAs although the focus is on reducing power consumption. Hollingworth said a shift to the 40LP process would compromise on speed too much but that the company took steps to limit power consumption: “We haven’t really increased the core performance from Stratix 3. The decision to that has come from the market. Every time we have designed a new family, we have asked people: where do you want to put the slider between performance and power? They used to say power. Then we found with 90nm that was no longer the case,” Hollingworth explained. “The power envelope has not increased for the device, but the density has. You can get twice the logic elements for the same power as the previous generation.”

To reduce leakage current when blocks are inactive, Altera is using back-biasing as well as the two-speed logic array introduced on the 65nm Stratix 3. There are two halves to the Stratix 4 family: one intended for general-purpose designs and one for communications products that add transceivers able to run at up to 8.5GHz.

Rather than using the 65nm process for HardCopy versions of the Stratix 3, which arrived comparatively late in the development of 65nm, Altera has opted to port mask-programmed designs to the more advanced 40nm process. It will be joined by a HardCopy that reflects the higher density of the Stratix 4. “For the first time, we are adding transceivers to HardCopy,” said Hollingworth. “We didn’t do that before because they were a little bit new.”

By jumping to 40nm for the HardCopy conversions, Altera expects to steal a march on the traditional ASIC business. Based on the average gate count figures provided by Gartner for ASIC starts, Hollingworth claimed the density offered by the Stratix 4 and both new HardCopy families easily exceeds what many electronics companies need. “In history, our largest sized parts have followed the industry average for ASIC starts,” he said, adding that the move to the latest process has surged beyond the average, which has grown modestly in recent years. “The mainstream for ASIC is still 130nm migrating to 90nm. We think we are two or three generations ahead of the mainstream,” he said. With the FPGAs, he claimed: “If you have a lot of memory, we should be very comparable on cost [with ASIC starts on the older processes]”.

Hollingworth claimed since 2002 the company has performed 160 tapeouts of HardCopy designs. “Nine out of ten of our top customers are using HardCopy,” he said.

To deal with the increase in mask costs, the company is putting the masks for two metals layers onto the same reticle. This has held non-recurrent engineering costs to less than $500,000 thousand dollars versus the $1m that would be needed for standard mask sets for a metal-programmed gate array. The tradeoff is in slightly more expensive wafers: “It adds 2 to 3% to the cost of the wafer,” Hollingworth said.

To try to entice developers of higher-volume products to use its parts, Altera is focusing more on the cost of HardCopy. “One of the things we are doing with HardCopy that we haven’t done previously is look at the package. Previously our aims has been to make the HardCopy devices form, fit and function compatible with the FPGAs. But to get into half million units, cost is more important. So we have started doing non-pin compatible versions,” he explained.

A high-end FPGA might have a 1152-pin package. “Previously, we would put [the HardCopy version] into the same package. For the highest volumes you would be at a significant cost disadvantage versus standard cell if you did not need that many pins. What we will do is create an 1152-pin version and then switch it to something like a 484-pin package.

“We will do a custom package if people really want that. Package cost can be 50 per cent of the cost of the device. Some of the multilayer packages are extremely expensive.”

Tools to support Stratix 4 designs will ship in June with the first parts to tapeout to TSMC at the end of the third quarter. The first device will be the GX230, which has serial transceivers and 230,000 logic elements. The second will be the part with transceivers and 530,000 logic elements. “We have got a lot of requirements in those areas,” said Hollingworth. “HardCopy will ship a year later; we really don’t have to do it earlier.”

Image: For its latest generation of Stratix parts, Altera will move to TSMC's 40nm process

Recent articles

Info Message

Our sites use cookies to support some functionality, and to collect anonymous user data.

Learn more about IET cookies and how to control them