Accellera sets up verification IP group

Accellera, the group that puts together a number of the standards used in electronic design automation (EDA), has formed a committee to look at standards for verification intellectual property (IP). The committee aims to define technologies and methods to build a modular and reusable verification environment.

The problem today, said Accellera, is that verification components and environments are currently created in different forms, making interoperability among verification tools or geographically dispersed design teams time-consuming and error-prone. By improving interoperability and removing the cost of having to repurchase and rewrite verification IP for each new project or electronic design automation tool, the VIP standardisation effort should lower overall verification costs and improve design quality.

“Accellera is addressing the electronic design industry’s need for a common standard for verification IP interoperability and reuse,” said Shrenik Mehta, chair of Accellera. “Our newest VIP technical subcommittee’s goal is to improve design productivity by making it easier to verify the design components with a standardised representation that can be used with various verification tools.”

The committee will focus on the use of verification IP with the SystemVerilog language. Accellera said participation on the subcommittee is open to anyone.

Image: Standardisation of the verification IP environment should speed up chip design

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