Synopsys decides graphics needed for logic synthesis
Synopsys has opted to give one of its most text-oriented tools, Design Compiler, a graphical makeover in an attempt to show logic designers how congested the physical design could turn out.
Steve Smith, senior director of marketing for implementation platforms at Synopsys, said most EDA tools are text oriented and it is especially the case for logic synthesis, where the input is in the form of hardware description languages and control scripts. But, he added that decisions made in the HDL and synthesis constraints can affect how badly congested some parts of the design can be in terms of the routing between logic gates.
“Three years ago, we introduced a technology called Topographical. It performs optimisation based on the cell sizes and timing of the interconnect: it was physically aware synthesis and an outgrowth of the work on Physical Compiler. However, the only people who used Physical Compiler were the physical designers. DC Topographical was an attempt to get front-end design engineers to think about physical constraints.
Smith added: “The main technology added was placement: it has very fast placement technology but is highly correlated to the actual place-and-route tools, and not just those from Synopsys. For a popular tool like DC, that was very important.”
DC Graphical, Smith said, goes one step further: “We have added global routing technology. It allows us to do congestion analysis. That is where the graphical term comes from: to visualise the congestion we need a layout viewer. It shows hot-spots and uses fly lines to show where nets cross over.
If the routing prediction shows too much congestion for comfort, the designer can tell the tool to generate a different type of circuit to use less interconnect overall or which allows the metal lines to be spread out further. For example, it might constrain cell selection to use more complex cells: this would use local routing layers more extensively and perhaps relieve the pressure on the middle routing layers where congestion is generally most apparent.
Smith said the reason for congestion becoming a logic designer’s problem lies in the evolution of chip design. “Now, they use a lot more fixed blocks,” he said. This forces the synthesised logic to fit oddly shaped spaces, which can aggravate the congestion problem. “We also did some optimisations for the memory guys, because they have very oddly shaped logic blocks, often very long and thin. It’s the same with disk drive controllers.
Smith added: “Over the years, we have been bring things forward from the back-end tools. Things are moving upfront because we can’t afford for things to go wrong sometime down the design path.”
Image: DC Graphical shows a 'heat map' of routing congestion in logic blocks