Delayed Virtex-5 parts go to sampling
Xilinx has started to ship production samples to customers of the last family of field-programmable gate arrays (FPGAs) in its Virtex-5 series. But the announcement comes almost a year after Xilinx expected to make it.
At the launch of the Virtex-5 in mid-2006, the first FPGAs to use a 65nm process, the company said it would perform public sampling of the Virtex-5 FXT, which integrate high-speed serial transceivers and PowerPC 440 processor cores, in the first half of 2007. However, first silicon did not arrive until the summer of 2007. The company performed limited sampling to key customers in December, said Per Holmberg, director of worldwide product marketing at Xilinx.
Holmberg said the delay lay “in the integration of the different capabilities; it took a little longer than expected. We are using a new, higher-speed transceiver.”
The Virtex-5 FXT doubles the speed of the transceiver provided by existing members of the range from 3.2Gb/s to 6.5Gb/s. Altera has supported speeds of up to 6Gb/s on its serial transceivers since the launch of the 90nm-based Stratix-IIGX family in 2006 and Xilinx had higher-speed transceivers on certain members of the Virtex-4 family. “The plan all along was to have two different types of transceiver. The transceiver in the SXT and LXT families is optimised for low power and ease of use. Then we would provide really high performance.”
With either one or two PowerPC 440 cores and serial transceivers design to cope with new interfaces such as Cisco Systems’ Interlaken, Xilinx has aimed the FXT at the communications market, also expecting to see pick-up in military and the audio and video broadcast business as that overlaps increasingly with communications. Xilinx has added logic to support the encoding schemes used by Interlaken.
Simon George, embedded specialist with Xilinx, said: “A lot of customers in communications are using PowerPC already and they want the backplane interfacing features.”
For the new family, the first of the 65nm-based FPGAs to include a PowerPC core, Xilinx has upgraded the processor from the 405 used in previous Virtex parts to the faster 440. It runs at 550MHz and includes memory-management unit and caches. To improve throughput, the company has put much more of the bus infrastructure into hardwired logic and included a five-way crossbar that allows four direct memory-access channels and the processor’s own memory requests to run in parallel.
“In Virtex-4, the whole memory subsystem was done in fabric. This time, we identified the key elements used in processor subsystems. Not only does it save FPGA resources, it increases performance.”
George noted that the crossbar runs at 260MHz: “Whereas in Virtex-4, we would be running at about 100MHz.”
The memory interface used by Xilinx is its own processor local bus (PLB), which now comes in versions for all the company’s embedded processors, including the MicroBlaze synthesisable core.
Image: Xilinx has put together reference designs based on the Virtex-5 FXT for target applications such as basestations