Deal puts leakage power reduction into TSMC flow

Design-for-manufacturing specialist Blaze DFM has cut a deal with the world’s largest foundry that will let TSMC subtly alter customer designs so that they consume less power.

The exclusive deal allows TSMC to use a version of Blaze MO to increase the length of transistor gates on circuits that are not timing critical to cut their leakage power. Blaze DFM and TSMC have worked with a selection of foundry customers on a trial of the Power Trim programme since the middle of last year.

The tool uses timing analysis to work out fast transistors need to switch on logic paths and, if they can switch more slowly, lengthen the gate by small increments. The changes are made during optical proximity correction (OPC), the technique used to ensure that transistor features print as intended.

Jacob Jacobsson, CEO of Blaze DFM said performing the changes at the OPC stage rather than during the layout generation phase allows greater precision in the gate tuning. “By doing it that way, the modifications available to you are different: you can be more aggressive in the changes that are made because you are much closer to what actually happens. If you try to do this on the design side, it may get flagged as a design-rule violation.”

Although some companies are offering the ability to tune gate length to reduce leakage STMicroelectronics launched a service recently the Power Trim service is the first offering to take a design tool and implement it as part of a foundry process. TSMC performs its own OPC, so is able to deploy the tool within its own processes.

The service does not require any major changes to the customer's existing design flow although the results of the analysis need to be fed back into the customer’s timing analysis to ensure that a projected change will not cause the chip to fail.

TSMC said two of the top five fabless semiconductor companies have already fabricated chips with this process option at TSMC and others are being added selectively during a phased rollout of the technology. The Power Trim option is available on TSMC process technologies from 90nm down.

Jacobbson said the deal could lead to other design modifications to improve manufacturability or device performance being performed at foundries. “We can use allowances that become possible because we are so close to the foundry,” he claimed. “I can see us doing other things with this concept.”

Image: A TSMC engineer inspects a mask, many of which now use OPC features

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