Actel focuses on I/O for low-power logic
Actel has updated its Igloo family of low-power field-programmable gate arrays (FPGAs) to have more flexible I/O than its predecessors and to cut power consumption in the I/O drivers.
The company has reduced overall I/O power by extending to the I/O cells the ability to ‘freeze’ on-chip bus states, at either logic-one or zero, with very little current consumption. This allows the FPGA to operate in a kind of sleep mode but keep certain peripherals active by maintaining control lines in an active state. Previous versions were designed to go into sleep without needing isolation but were not designed to preserve on-states on I/O lines.
Ranging in logic capacity from 30,000 to 125,000 gates, the Igloo Plus family has three 1.2V devices that have more I/Os per device than predecessors and support four I/O banks for independent level shifting. Actel said the use of multiple banks helps the device to better support different voltage levels, useful for bridging between application processors and application-specific standard products (ASSPs), where differing I/O standards and voltages may be used. Igloo Plus devices support level shifting between 1.2-, 1.5-, 1.8-, 2.5- and 3.3V I/O standards.
In the latest devices, Actel has added Schmitt trigger inputs and hot-swap support. The Schmitt trigger input delivers greater noise immunity in the circuit, enabling designers to safely identify an input signal that rises slowly, such as a keyboard or human touchpad. The hot-swap capability was put in for applications such as portable media players and games, where solid state mass storage modules and human interface controllers are often connected and disconnected from the system while powered-up.
The original Igloo devices were derived from Actel’s ProAsic3 family, using a lower voltage level 1.2V instead of 1.5V and a sleep mode that freezes the state of the FPGA. It takes about 1µs to wake from the sleep mode.
Image: The Igloo Plus has more I/O pads than its predecessors