Qimonda switches tracks in push for DRAM density
German memory maker Qimonda is to shift to a new architecture for dynamic random-access memories (DRAMs) in an attempt to leapfrog its larger competition in terms of density and cost efficiency
Qimonda, which has up to now relied on a trench capacitor design, will move to a 'mainstream' stacked capacitor approach that uses buried wordlines to improve density.
Kin Wah Loh, CEO of Qimonda, told analysts in a conference call: "This roadmap will take us down to 30nm and allow us to go to a 4F2 cell."
Currently, Qimonda's memories use a bit cell that measures 8F2 F being the minimum feature size on a given process. Other companies in the market, such as Micron, have introduced 6F2 cells, which has allowed them to produce memories with smaller die sizes, and reap more chips from each wafer. Kin Wah claimed the buried-wordline approach provides the key to being able to produce a 4F2 by the time the company moves to a process with minimum feature sizes of around 30nm two generations from now.
In the meantime, the company will spend €100m on new equipment to cope with the buried-wordline structure and run memories based on its existing 58nm process in parallel with the new architecture, which will run with minimum sizes of 65nm. "The full manufacturing transition [to buried wordline] will take place with the move to 46nm in the second half of 2009," claimed Thomas Seifert, chief operating officer of Qimonda.
Kin Wah claimed the move to the 65nm buried-wordline technology and, for the moment, a 6F2 bit cell would lead to a die size of 55mm2 for a 1Gb DRAM. The company's 70nm technology produces an 80mm2 die, said Seifert, noting that the shift from 8F2 to 6F2 provides a density improvement of 30 per cent on a given process.
"55mm2 is about as competitive as it gets in this technology node," he said.
"We will be ramping 65nm in the second half of 2008. We plan also to make 46nm also with the 6F2 cell. That will more than double the number of gross die per wafer," claimed Kin Wah. He said the €100m for capital equipment is on top of currently planned spending for migration to new processes. For all manufacturers, sub-45nm processes will call for more complex lithography techniques such as immersion and double patterning.
Seifert claimed the company's new approach, with the long wires used to access bit cells buried in the silicon substrate, is more power efficient than existing architectures where the wordlines run past the contact vias that connect the DRAM capacitor to its selection transistor.
"Capacitive coupling between the bitline and the wordline is greatly reduced," added Frank Prein, senior vice president of technology.
Kin Wah said the 65nm buried-wordline technology will be used to make mainstream DRAMs as well as speciality memories for the embedded-systems market.
Qimonda is not alone in trying to develop 4F2. Elpida Memory said last year that it plans to have a 4F2 bit cell in place by the 30nm generation and Samsung has reported a possible candidate for its use at technical conferences.
Analysts questioned the timing of Qimonda's announcement one that provided an unprecedented level of information about the company's future plans, according to Kin Wah in the wake of speculation about possible partnerships and mergers in the troubled DRAM sector. The market fell by almost 40 per cent last year and analyst firm IC Insights said DRAM revenues are likely to shrink by a further 7 per cent this year.
Image: Qimonda plans more cost-efficient DRAMs for use in PC memory modules as well as in embedded systems