Mentor takes readymade route to chip checks

Mentor Graphics has reintroduced to the market a pair of verification technologies that the company bought recently, packaging them as readymade components rather than trying to sell the underlying software as tools.

Mentor bought UK-based Spiratech and US startup Lighthouse as additions to its verification line-up. Spun out from mainframe maker Fujitsu-ICL, the people behind Spiratech developed many of the concepts now used in transaction-based verification and system-level design. Lighthouse developed novel graph-based algorithms that can provide more intelligent control over how a testbench produces the vectors it uses to exercise a design. Spiratech built its business around a specialised form of C designed to model electronic systems.

“The idea we worked on was how to bring this stuff to market,” said John Lenyo, . “Lighthouse sold a compiler where you were meant to figure out your own graphs. That mode is still available but that is not our primary mode for selling the technology. With Spiratech, we are not sure the world needs another language.”

The Lighthouse technology has been reintroduced as Infact a testbench-automation tool that provides readymade algorithms for verifying commonly used buses and peripherals. With the Spiratech technology, Mentor has built models of commonly used standard intellectual-property (IP) cores. They can be used to model those components at a high level, using untimed function calls, or with detailed timing for hardware-level verification tasks.

“You have, say, a model of ARM’s AHB [Advanced Hardware Bus] with Spiratech’s engine inside. You push the button and get the level of abstraction that you want to model at,” claimed Lenyo.

Lenyo said that one of the issues that Mentor had to solve for Infact was to get the algorithmic vector generators for each core to work together in a full-chip simulation. “The roadblock was how to synchronise them so they don’t generate incoherent data,” he said.

Image: Mentor's additions should speed up the production of useful digital test vectors

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