TSMC combines masks for cheaper prototypes

Taiwanese foundry TSMC has launched a service intended to cut the spiralling cost of making the masks needed to produce chips on 90 and 65nm processes.

Taiwanese foundry TSMC has launched a service intended to cut the spiralling cost of making the masks needed to produce chips on 90 and 65nm processes.

The cost of mask-making has risen dramatically over the last ten years, driven by the sophisticated techniques needed to define features as small as 65nm across using light sources of three times that wavelength. The cost of a complete set of masks, generally numbering more than 40 individual masks in a sub-130nm process, has climbed to almost $1.5m. The situation is expected to worsen as processes head to 45nm features and below. These costs can be absorbed by chips made in high volume, but are punishingly high for those that will not sell in the hundreds of thousands.

"We felt there was a need for an interim cost solution that could be used for low-volume production," said Gareth Jones, director of business operations for TSMC Europe.

TSMC's approach, intended for prototyping and low production volumes, is to put four masks onto one lithographic reticle at the cost of slowing down production. Most chip designs are substantially smaller than the reticle, which has an area of around 600mm2. So, the chip will generally be reproduced across the reticle to try to fill the area as much as possible. This lets the lithography tool print the image on the reticle across the wafer using the minimum number of steps and keep throughput high. Normally, chipmakers like to have a throughput of more than wafers per hour.

By putting the masks for different layers onto the reticle, the tool has to use a larger number of steps to fill up the wafer, which slows the process down. Jones said the effect on throughput with the multilayer mask (MLM) technique, is "considerable". However, the approach slashes the total number of masks that need to be made. For chips of around 100mm2, more than four masks could be placed on one reticle, in principle. However, Jones explained that the shared masks have to be of the same grade, so that those needed to define gate-level features are on different types of mask to those needed for the metal layers that go on top. This limits the number of shared masks on a reticle to four, he said.

"There is a cost saving on mask costs but a cost adder on wafer price," said Jones. "What drove us to offer MLM is that we see a significant number of tape-outs that never get into high production," he added. Some are used purely for sampling to customers, for verifying designs or to address new markets with uncertain demands.

Like other foundries, TSMC offers a multiproject wafer service for prototyping designs and some suppliers, such as Mosis, will produce run-ons beyond the base set of 25 wafers to support chipmakers who want a few hundred devices for sampling. However, these services run on set schedules and are not economic for higher production volumes. "The beauty of MLM is that you can populate the full wafer with your design. You can launch anytime and it is more cost-effective than single-mask tooling for low volumes. It does provide a cost-effective solution for volumes of 100 to 200 12in wafers, depending on die size," Jones claimed.

Image: A TSMC engineer inspects a reticle

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