OCP-IP readies debug spec

The on-chip interconnect standards group OCP-IP has passed the specification for a new debug port to member review. The specification describes an approach to a standardised debug socket that can be added to all cores and IP blocks and which is intended to be compatible with other industry standards efforts addressing debug and related on-chip issues.

The on-chip interconnect standards group OCP-IP has passed the specification for a new debug port to member review. The specification describes an approach to a standardised debug socket that can be added to all cores and IP blocks and which is intended to be compatible with other industry standards efforts addressing debug and related on-chip issues.

Work on the specification was completed by the OCP-IP Debug Working Group led by Texas Instruments, HDL Dynamics, MIPS Technologies and Pixelworks with the co-operation and contributions of several other sponsor member companies and other independent organisations.

The document describes an overall debugging framework as the basis of the OCP debug interface. In the same way that the OCP data framework is a functional superset for various bus interfaces and data structures, the OCP debug framework defines an OCP debug interface socket that can connect to a superset of debug implementations, including those developed outside of OCP-IP. The specification loosely defines requirements and a set of debug signals at the OCP socket and fabric levels, leaving much of the specific options for implementation open to IP and tools vendors.

Commercial and licensable instrumentation IP and tools that support many of the debug socket interface options are available today from OCP-IP members, the group said.

Image: The specification should make it easier to debug complex chips

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