Mentor gets third-party checks for system-level design

Mentor Graphics had decided to incorporate a design checker from Calypto Design Systems to round out a system-level design flow based on its Catapult C synthesis tool

Mentor Graphics will be working with Calypto Design Systems to fill in the missing link for a flow that can take designs expressed in C and turn them into synthesised hardware circuits.

The system-level design flow built by the companies includes Mentor's Catapult C synthesis tool and Calypto's SLEC sequential equivalence checker. The combination has been run in trials at a number of customer sites and by the Japanese research consortium STARC. The SLEC tool is used to formally verify that the RTL produced by Catapult C is functionally correct.

"With high-level synthesis tools, it is essential to verify that the high-level C description is functionally the same at the tool's RTL output," said Haruhisa Kashiwagi, senior manager of a STARC system-level design project. "During STARC's ASUKA II project, we evaluated the Catapult C Synthesis/SLEC flow from Mentor Graphics and Calypto Design Systems. Using several examples, we have verified that the RTL generated from the Catapult C Synthesis tool has the same functionality as the high-level source code. We were able to accomplish this in a short period of time, and we ascertained a seamless integration between the two tools."

Calypto CEO Tom Sandoval claimed: "Customer experience with the SLEC/Catapult C flow confirms that ESL synthesis and verification is ready for mainstream design. STARC's project demonstrates the interoperability and productivity benefits of using an ESL flow for large-scale hardware design."

Image: The use of more automation in system-level design should speed up the creation of complex chips.

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