Analysis: All change for 45nm
In the rush to 45nm, chipmakers find themselves facing difficult choices. They need to change the way they manufacture devices, but without pushing up costs.
When Intel said last year that its move to metal gates in transistors was the biggest change it had made in 40 years of chipmaking, it was not the only alteration that the company decided on for its 45nm process.
The semiconductor manufacturing process, which underpins the 16 different microprocessors that the company launched at the Consumer Electronics Show this month, marks a radical shift in the way that devices such as these are designed and made. But some companies are hanging back from making changes along the lines that Intel has chosen, hoping that they can develop cheaper alternatives.
Cost is the factor that lies at the heart of the move to 45nm: companies touting their new processes at the recent International Electron Device Meeting (IEDM) in Washington DC were keen to emphasise how tightly they could pack elements such as memory cells and the transistors that lie at the heart of all logic circuits.
One of the problems with metal gates is that their implementation can almost double the number of steps needed to produce the two types of transistor that today's complementary metal-on-semiconductor (CMOS) demands. The two types of gate need different metals and processing steps.
Kaizad Mistry, director of logic technology integration at Intel, claimed the company's process has no more major steps than its existing 65nm process. Intel needed to introduce one step to add the different metals, but another step had been removed, he said.
However, other chipmakers plan to work on an approach that will involve only one type of metal so that they can avoid introducing any additional and costly process steps. A move to a single metal would cut costs, claimed Kazunari Ishimaru, director of engineering and project leader at Toshiba America and currently on secondment to IBM's TJ Watson Research Center. He noted that the move would make it easier to decide whether to switch from poly-crystalline silicon (polysilicon) to metal gates.
IBM's project manager for high-k and metal-gate technology, Mukesh Khare, told Engineering & Technology that IBM will use metal gates on its own 45nm process, intended for use by its mainframe-computing group, but that the Common Platform process - the one that it shares with partners such as Chartered Semiconductor Manufacturing and Samsung Electronics - will press ahead with conventional gates made using polysilicon.
IBM aims to have a single-metal approach ready for the 32nm that will follow in roughly two years to keep costs down. Khare said IBM's partners insisted on a low-cost process. "The partners that we have provide us with all this great input: that the process must be the cheapest," he said.
CC Wu, deputy director of logic technology development at Taiwanese foundry TSMC, claimed that the company was able to use conventional polysilicon gates - needed for low-cost - in its 45nm process and still get high performance. Even for its early work on 32nm, the company pressed ahead with polysilicon rather than metal gates.
Mistry was more coy about other changes that Intel made in developing the process used to produce the latest batch of processors, codenamed Penryn. These revolve around the way that the tiniest features are printed onto the chip.
Answers to some of those questions were filled in thanks to reverse engineering. Canadian analyst firm Chipworks has been examining the first of Intel's 45nm-based processors to try to work out how the world's largest chipmaker has approached the problem of deploying metal gates and making such densely populated parts.
To improve the layout density of its 45nm process, Intel has moved away from using conventional round vias to connect the transistor source and drain to the first layer of metal interconnect. Instead the company has decided to use what it calls trench contacts.
Dick James, senior technology analyst for Chipworks, said that, because of the trench contacts, the layout of the processor "looks very different" from any other chip on the market.
The contacts or vias used to connect the transistor inputs and outputs to each other in circuits are normally round. However, it has become progressively more difficult to produce these shapes reliably because the wavelength of light used to define them on a photoresist is several times larger than the features themselves. Diffraction effects mean that the shapes of neighbouring vias interfere with each other, causing some to disappear under worst-case conditions.
Intel's trench contacts are long and thin and laid out in a much more regular array, said James. This makes the effects of diffraction more predictable and improves the conductivity of the contacts. It also means the company can use a technique called double patterning to avoid having to go to lithography equipment that immerses the wafer in a liquid to boost the refractive index and obtain better resolution. Chipmakers such as TSMC favour immersion lithography, but some are concerned about bubbles introducing defects.
Intel senior fellow and director of process architecture Mark Bohr confirmed that the trench contacts were used exclusively at the base layer to overcome the increasing difficulty of dealing with conventional round contacts.
James said that the rectangular contacts would probably increase the capacitance between them and the nearby transistor gates, leading to interference between them, a factor that designers would have to take account of. Bohr agreed the capacitance did go up but not enough to have a major effect on design other than the new layout techniques needed to define the trench contacts.
"It speaks to the advantage of having both circuit design and manufacturing," James noted.
The question is how many more big changes will be needed to chipmaking processes to stay on track for future increases in circuit density.