Electronic design automation: grand design, micro scale

13 October 2014
By Martin Courtney
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A model of silicon ICs soldered onto a circuit board

This model of silicon ICs soldered onto a circuit board was meshed using the enhanced automatic sweeping feature

Valerio Marra, Comsol Inc

‘The real opportunity is to provide development infrastructures for customers to create their own models’ 

KiCad screenshot

KiCad is an example of an open-source EDA software suite for the creation of professional schematics and PCBs

Sherry Hess, VP of marketing at NI AWR group

'EDA performs numerous tasks and provides feedback that enables designers to identify design challenges'

Board-level resolution tool

EDA tools enable designers to find and fix any design flaws saving costly mistakes

Screenshot of NI's automated circuit extraction tool

NI’s automated circuit extraction tool uses layout-based models to identify complex interconnects

Aart de Geus

Aart de Geus, Synopsys: focus would remain on silicon

Krishna Balachandran, Cadence Design Systems

'The idea is to decouple the design from the power information'

Electronic design automation software for engineers of integrated circuits has to keep pace with a fast-moving range of requirements being created by a dynamic and demanding industry.

Electronics engineers engaged in the design of integrated circuits, systems on chip (SoCs), application-specific integrated circuits (ASICs) and other semiconductors face a complex, time-consuming task. It's one that calls for all the help they can get from electronic design automation (EDA) software when it comes to simulating and testing their wares prior to fabrication, and with the constant flow of innovation in the integrated circuit (IC) market, the producers of software design tools are upping their game in order to keep pace.

"IC manufacturers understand that wasted design cycles are costly, whether on gallium arsenide (GaAs), gallium nitride (GaN), or silicon – [and] as IC process sizes shrink, the complexity of the design grows," says Sherry Hess, vice president of marketing, AWR Group at National Instruments (NI). "EDA tools are necessary to save time, reduce cost, and shorten design cycles, because they automate numerous tasks and provide feedback that enables designers to identify and correct design challenges before entering the costly prototype and manufacturing phase."

Time-saving is also a critical factor. "Our customers claim to speed up the design process by anything from 20-80 per cent depending on the application and [available] resources," explains Valerio Marra, technical marketing manager for Comsol Inc. "Sometimes it is not much, but 20 per cent of a prototype can save a lot of money and even where it [the model] is experimental, you can try to understand what is going on and perform tests. It is not the ultimate solution, but it is a helpful tool."

With silicon manufacturers and device makers looking to pack an increasingly-powerful processing punch into ever-shrinking devices while simultaneously reducing their electricity consumption, building efficient power management into initial semiconductor design has become something of an obsession for the current generation of IC designers, but it is no new concern.

Krishna Balachandran, director of low-power product marketing at EDA software and tools vendor Cadence Design Systems, says that power management has, in fact, been a design issue for at least 15 years. The difference is that only a few mobile application developers and semiconductor companies were previously focused on low energy usage, but now a far broader range of players are taking it more seriously.

Cadence has steadily introduced new power management features into its software, including support for the IEEE 1801 Unified Power Format specification – a common standard to describe lower power design intent in multi-vendor design flows, whose definition was led by Nokia, Texas Instruments (TI), and EDA software specialists Magma Design Automation (Synopsys) and Mentor Graphics.

The latest iteration of the specification – revised in 2013 and additionally supported in EDA software from Mentor Graphics, Synopsys, Aldec, and Docea Power – attempts to improve support for power modelling, implementation and verification through the IC design lifecycle, paying specific attention to the incremental improvement of a design as more implementation detail is added without requiring engineers to rewrite command scripts.

"The idea is to decouple the design from the power information so that the same design could be applied to different power architectures. This would enable low-power and high-speed applications to use different power management techniques," says Balachandran, whose company has also introduced capabilities such as power-aware simulation and emulation to allow designers to experiment with different power modes in order to tune energy consumption in the context of actual software scenarios.

"Depending on the design, emulation can be a hundred times faster than using a software simulator – to verify power intent and run a lot more tests and get better coverage for the device overall. The greater speed allows more scenarios to be explored and so identify power issues in the context of the full system early in the design process."

FreeScale Semiconductor is an international company specialising in the design and production of embedded microcontrollers, microprocessors, digital signal controls, sensors, radio frequency (RF) power, and power management ICs for the automotive, networking, industrial, and consumer markets. Freescale used Cadence's Encounter Digital Implementation software to finalise (or tapeout) the design of its 1.8GHz 64-bit 12-core QorIQ T4240 system-on-chip (SoC) communications processor destined for use in telecommunications and enterprise networking equipment.

Wireless applications

Successful IC design for wireless or mobile communications applications also relies on being able to minimise crosstalk between different frequencies and channels, and stay within limits on spectral emissions and signal interference set by telecommunications standards.

Semiconductor company TriQuint used NI's AWS Microwave Office and Visual System Simulator software tools to design an Edge/GSM power amplifier for use in a mobile handset, accurately characterising the amplifier's circuit performance at system level, and predicting adjacent channel power ratio measurements (ACPR) to minimise the effect of spectral spreading to ensure compliance.

COMSOL Multiphysics finite element analysis (FEA) software is used in a wide diversity of applications – one of which involves the analysis of stress and potential breaking points in flexible printed circuit boards (PCBs) where crosstalk between the layers can adversely affect the strength of the structure and generate heat that degrades the conductivity of the circuit.

"I carry one signal, and you carry another one, and that creates crosstalk and interference – and vice versa," explains Marra. "The question with using high frequencies is how much heat that generates. You might decide to use copper, but what happens if conditions change – how does that affect the electrical conductivity of copper, and can you simulate that?"

In other applications of Comsol's software, its MEMS (micro-electrical mechanical systems) module is employed in the design of micromirrors for the digital light processing (DLP) chips used in digital video projection, while the RF module is used to build antenna arrays for GPS chips.

Both EDA and FEA software is expanding to encompass new materials and processes as manufacturers look to lower-cost, more flexible or less power-hungry materials to replace silicon within semiconductors.

"Metals cannot cover everything," adds Marra. "The real opportunity here is to provide customers with the development infrastructure to create their own models, using their own materials."

Silicon alternatives

US light-emitting diode (LED) manufacturer Cree used NI's AWR Microwave Office to design power amplifiers that use gallium nitride (GaN) as the semiconducting material, for example. This includes the CDPA21480 Doherty amplifier, which delivers peaks of 480W and average 80W of RF power for wideband CDMA (WCDMA) networks operating in the 2170MHz UMTS waveband. Engineers were able to optimise the Doherty's performance over a range of power levels using individual source and load-pull measurements on the amplifier, leading to more accurate models that reduced design time by up to 70 per cent using linear frequency domain and harmonic balance simulation through electromagnetic analysis.

CoolCAD Electronics is a custom electronics design firm that specialises in unusual, or non-mainstream, design applications including cryogenic and radiation hard electronics and silicon carbide (SiC) power hardware. The company is working closely with Nasa to develop design tools and methodologies that can help the agency perfect electronic components for use in extreme space environments characterised by very low temperatures and radiation effects.

CoolCAD's SiC Power Electronics Virtual Design Platform is specifically orientated towards SiC devices and ICs, and has been used in circuit and systems simulations carried out by commercial vehicle manufacturers such as General Motors and Ford, and military hardware specialists including General Atomics and Raytheon.

Many ICs also use light to transmit and process signals, with both Phoenix Software and Lumerical Solutions specialising in the supply of photonic circuit design software to manufacturers and research institutions. Lumerical's products are widely used in the design of CMOS image sensors for digital cameras, solar energy and photovoltaic cells, optical networking applications and nanoscale lithographic surface analysis and defect detection in semiconductor manufacturing. In the solar application, the software is used to model plasmon resonance in nanoscale metallic arrays deposited on the surface of thin-film silicon cells to enhance their conversion efficiency.

Cross-industry integration

Hess says that this greater tool integration and 'co-opetition' between EDA vendors is the way forward for the industry, with interoperable 'application specific' products focusing on a specific element such as design synthesis or optimisation algorithms becoming the norm.

Though something that EDA software companies have historically not been especially good at, there are signs that the growing demand for increasingly complex designs from different vertical industries and a broader customer base expanding beyond semiconductor companies is now providing the necessary impetus. NI worked with engineering simulation software vendor Ansys to integrate the latter's high frequency structure simulator (HFSS) into NI's AWR Microwave Office high frequency circuit design package to help designers simulate microwave circuits more quickly and accurately, for example, whilst Synopsys worked with MathWorks to improve their respective design verification capabilities.

Founded in 2010, the Si2's Open process design kit (OpenPDK) Coalition also set itself the task of defining a standard which would allow an agnostic OpenPDK to be created once and then translated into specific EDA tools and foundry formats to aid its portability across different software tools. Si2 (full name: Silicon Integration Initiatives) is an industry body whose members include Globalfoundries, IBM, Intel, Samsung, and STMicroelectronics, as well as Mentor Graphics and Synopsys, all of which are workingto develop reference implementations able to store and process data – database resolution layers, purpose, material and display information – in APIs (application programming interfaces) that can be transferred between EDA tools.

"Integration of thermal tools, design rule checking (DRC), layout versus schematic (LVS), HPC and standards bodies like Si2 with its open PDK – all are making a big difference by removing barriers designers previously faced when moving from one disparate tool to another in order to construct their own design flows/environments to meet the evolving needs of today's RF/microwave ICs," believes Hess.

Marra says that the IC design process has a better chance of being more accurate if results from multiple tests and simulation can be compared and correlated. That includes using more than one EDA/FEA tool for the job: "If you want to be successful [in your design], you have to use all the tools out there, not just rely on one – but that creates another issue, which is that sometimes different tools cannot communicate." 

Further information

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Power management

FinFET development and the next generation

Some EDA companies are looking to introduce support for finFET multi- and tri-gate transistor architectures into their modelling software. FinFET technology is forecast to eventually replace traditional metal oxide semiconductor field effect transistor (MOSFET) equivalents. This is because it improves power consumption by reducing current leakage and producing less static power when compared to 32-nanometre circuits and planar transistors; which means that semiconductor engineers can potentially achieve better performance at the same power budget, or equal performance using much less energy.

Cadence Design Systems, meanwhile, is working closely with South Korean manufacturing giant Samsung on its 14nm foundry logic process and design infrastructure for advanced mobile SOC applications for example, though Krishna Balachandran acknowledges that for now this remains a work-in-progress. Samsung announced that it would provide SKILL-based process design kits (PDKs) for Cadence's Virtuoso Advanced Node for sub 20nm IC design in February 2013.

"It is not just Samsung, but other companies [which include ARM, Taiwan Semiconductor (TSMC) and Global'foundries] getting ready to support finFET-related issues associated with printed circuits and make sure [EDA] tools can handle finFET design types," he says. "It is not just a concept or research but a state of readiness, but as always there is always more work to be done."

TSMC announced that it would begin manufacturing finFET-based 3D chips using a 16nm process in December 2013, albeit initially only in small quantities, with EDA vendor Synopsys particularly enthusiastic about meeting the task of tuning its EDA tools to finFET manufacturing processes, and preparing libraries and memory compilers to ensure successful design flows, and is working to enable its Galaxy Design Platform to support Intel's latest 14nm and 22nm Tri-Gate technology

"The fact there is such a push on to finFET has brought a wave of work on Synopsys but that is not a negative, it is a positive, an opportunity to drive the state-of-the-art forward," Synopsys chairman and CEO Aart de Geus told analysts in August 2014, though he stressed that the focus would remain on supporting fully depleted silicon-on-insulator (FD-SOI) 28nm planar transistor processes until finFETS became 'economically more mature'.

Case study

FEA feeds from IC design to production

California-based Lam Research Corporation supplies the manufacturing equipment which the chip makers then use to build the nanoscale ICs incorporated into smartphones and other portable devices which, due to their size and battery limits, have strict constraints around power usage.

Specialising in thin film deposition, plasma etch, photoresist strip and wafer cleaning solutions for front-end wafer processing and advanced packaging applications, Lam's Computational Modeling and Reliabilty Group uses a number of different simulation and finite element analysis (FEA) software tools to help design and test its new products.

One of these is COMSOL Multiphysics, which was employed to study the effects of wafer deformation on photolithography, a chip-making process which is similar to the development of photographs, and which shines light through a mask onto a photosensitive surface in order to deposit or etch multiple layers of semiconducting material in a specific pattern until the IC is complete.

With size requirements down to 22nm or less, even minor wafer distortions can cause misalignments that affect performance. Allowable deviations from the required pattern, or overlay errors, on today's advanced CPUs are generally around 10nm. Using COMSOL Multiphysics, Lam analysts were able to identify and precisely correlate the degree of wafer bow during the manufacturing process for example, without requiring a difficult and time-consuming testing process based on trial and error.

Lam also built COMSOL simulation models to measure the stiffness of amorphous carbon, an elastic material used to build temporary trenches into which semiconducting material is then layered to form the metal interconnects that link a CPU's transistors, which is susceptible to buckling.

Applying Young's modulus (a measure of the stiffness of an elastic material) and Poisson's ratio of transverse to lateral strain, analysts were able to compare theoretical results with experimental values, determine an appropriate adjustment factor and use a simulation to predict when and how buckling would occur.

Elsewhere Lam engineers used simulation software to design the heating and cooling channels for the rings that distribute gas into a sealed chemical vapour deposition (CVD) chamber. These must be kept at a consistently uniform temperature in order to prevent microscopic particles breaking off and causing defects on the substrate.

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