Chipmakers are jostling for position to lead the race for circuit density on silicon as they head beyond the 32nm generation.
Chipmakers vied for the prize of densest process at the International Electron Device Meeting (IEDM) held in San Francisco in mid-December, using last-minute switches to put forward their best results and demonstrate that even as far as 22nm conventional transistor structures can still work.
TSMC switched its presentation at the last minute to present results obtained for what the company calls its 28nm process, and Intel secured a late paper position in an already crowded session on advanced CMOS technologies. IBM tried to go one step further by demonstrating that it should be possible to scale SRAM memory cells as far as 22nm: the process node due to arrive in 2011. Others, such as Toshiba, sought to show that processes using less aggressively scaled transistors could provide high density and, perhaps more importantly, the low-power performance that portable and consumer designs need.
At the same time, many of the disclosures skipped over important details as manufacturers seek to protect their trade secrets at a point where the correct choice of materials could prove make or break decisions in their respective futures.
IBM, Intel and TSMC talked about their use of high-k, metal-gate processes. But none of them went into detail about the materials that they used in their gate stacks.
In his presentation, Sanjay Natarajan, a member of Intel's logic technology development group, offered metrics but - perhaps not that surprisingly - little detail on how they had been achieved. Indeed, of four questions tabled later by IEDM delegates, some were not answered at all. None was answered in its entirety.
Since the late 1990s, determining how the name relates to the actual measurements and therefore the density of a process has been relatively straightforward. LSI Logic used to confuse matters by insisting on quoting the actual gate length instead of the drawn length. Diffraction meant that the actual length was generally a little shorter than the drawn dimension. By quoting this measurement, LSI could pretend that its process was more advanced than the competition. In practice, its processes were comparable to those launched by other companies at the same time.
One factor that put paid to the LSI approach was the arrival of optical proximity correction (OPC) and phase-shift masking (PSM). This made it possible to shrink the gate length, and push up the performance, of transistors much more quickly than Moore's Law scaling would imply. The direct link between process-node name - such as 130nm or 90nm - and gate length was lost and the convention became more closely associated with the pitch of the metal lines used to connect them.
The International Technology Roadmap for Semiconductors (ITRS) published by Sematech now describes processes in terms of the metal pitch. To make it easier to align those numbers with the commonly used process names, the ITRS talks about half pitch. But it's a recognition that the density of the bottom layers of the interconnect stack control density more than the gate length.
There are two ways of measuring gate pitch. One is to look at the pitch of metal lines where vias never lie side by side. Vias are thicker than the metal lines themselves, so need more space. The staggered arrangement provides the densest possible configuration, often exploited by memory designers to pack their six-transistor cells into the smallest space possible. This is the number normally quoted in the ITRS.
However, the side-by-side configuration is important for logic density as it determines how small a transistors can be made, as the vias leading to the source and drain will often straddle a gate and the via leading to the gate contact itself is offset. How small you can make this contacted gate pitch generally will largely control the density of a process.
In SRAMs and dense logic, you cannot entirely decouple metal pitch from gate length, as Bala Haran of IBM Research explained in his description of how the team designed what is currently the world's smallest SRAM cell. He explained that the industry has scaled gate pitch consistently over past generations whereas the same has not happened for gate length.
For about ten years, process engineers were able to take advantage of the use of OPC and PSM to shrink gates more rapidly than anticipated in the late 1990s. Even though concerns over power consumption, particularly with leakage power, forced a slowdown in gate-length reduction, there was still some headroom for gate-pitch scaling to continue through the 65nm, 45nm and 32nm generations. Haran said the industry has now used up all that space.
"We really have to scale the gate length if we want to scale the gate pitch," said Haran. "With previous [process] nodes, we had the luxury of not scaling the length because we had sufficient space to land the contacts. The gates are now in such a tight space that we have no space to land the contact."
For the anticipated design rules of a 22nm process, the gate has to be 25nm or shorter, said Haran. Not only that, engineers have to find ways of reclaiming area taken up by spacers that are used during manufacture to selectively dope the parts of the channel closest to the drain and source contacts. These regions of high doping are needed to control leakage - without them, the transistor would never turn off properly. A further problem, Haran said, is that scaling the contact itself is tough because yield suffers. "As you shrink, you start losing vias," he explained.
"The next problem is: how do we metalise very small vias with high aspect ratios?" Haran asked. The vias have high aspect ratios because horizontal dimensions have scaled but transistor heights have not. The IBM engineers took their cue from changes to back-end processes, replacing tungsten with higher conductivity copper, although the metal has its problems.
"People are very concerned about [copper] poisoning the device and, if you look at the back-end processes, we are already at the limit of what we can do with the copper-seed process. So, we did it using advanced liners," said Haran, explaining that the depositing ruthenium from a vapour into the via made it possible to scale down the thickness of the copper seed layer on which the actual copper plating forms.
The result of IBM's work was a six-transistor SRAM cell that has a short side no longer than the gate of a transistor from the 180nm generation introduced at the start of the decade. "We are able to demonstrate a 0.1µm2 SRAM cell," Haran claimed. "And we have excellent static noise margin: 220mV at 0.9V."
The IBM team developed some processes to minimise variability, which has become a major concern to SRAM designers. In the IBM 22nm process, static noise margin - which determines how sensitive a cell's contents are to electrical noise - is only 12 per cent lower than that of the 32nm technology that is due to go into production later this year. But the big problem is with cells that, thanks to variations in how the transistors are made, show much lower noise margin.
"We looked at the statistics for several hundred functional cells. Most of the cells had a static noise margin of more than 150mV," Haran claimed. "So, we decided to build an even smaller SRAM with exactly the same layout. The 0.09µm2 cell is 30 per cent smaller than the smallest cell previously built.
"We were able to demonstrate a 0.09µm2 with a static noise margin of 160mV. This is adequate for cell operation and proves that we can get adequate noise margin using the same device and design rules."
SRAM density was a prime focus for TSMC on its 28nm process, which is due to go into production early next year.
Ahead of IEDM, TSMC claimed that its presentation would focus on a 32nm high-k, metal-gate process. On the day, Carlos Diaz, director of advanced technology at TSMC, talked instead about the 28nm version of the high-k process which will be an option rather than the default technology for that node.
"High-k, metal-gate enabled us to scale the transistor technology. in a more healthy way But we believe this technology offers a limited advantage [over a silicon oxynitride-gate process], particularly in architectures that are back-end dominated," Diaz claimed.
Where parasitics such as interconnect capacitance dominate in a design, TSMC is working on the basis that a conventional silicon oxynitride-gate transistor will do just as well as one based on a high-k process and will be cheaper to make.
For its 28nm high-k process, TSMC claimed an SRAM cell size of 0.13µm2, smaller than the 0.17µm2 size quoted by Intel for its respective 32nm process. However, in terms of gate pitch, the situation reversed. Intel's Natarajan said the contacted gate pitch was 112.5nm: "The tightest recorded for any 32nm process." And it was ahead of TSMC's claimed length for its 28nm process of 117nm.
Intel did not respond directly to TSMC's surprise 28nm disclosures. Instead, Natarajan used his IEDM presentation to rebut claims that its gate-last strategy since 45nm is more expensive and yields below rival gate-first techniques - the ones to be used by IBM and TSMC.
"It adds just 4 per cent to process costs [at 32nm], just as it did at 45nm," he said. "We believe that is well justified for the performance leadership it enables."
Natarajan added that yield at 45nm had been the best for any process under gate-last.
He said that test runs for 32nm were following the same "two-year cadence on yield learning", suggesting so far that the company will achieve comparable yield on the new process as for the 45nm version when it enters volume production in the second half of 2009.
Diaz said the results obtained so far at TSMC with the 28nm process meant "we are pretty much on track to support 28nm volume production".
High-k but no metal for Toshiba
In an iedm session dominated by 32nm processes, a 40nm process presented by Toshiba seemed not just one generation behind but a bit more than that if you compared its headline figures with the 45nm technologies described by Intel and TSMC in 2007. But a closer inspection reveals a process that has more behind it.
When Toshiba says it's a 40nm process, the company means the gate measures 40nm. This is a good 30 per cent longer than the minimum gate length quoted by Intel and TSMC last year and puts the transistor more in line with a 65nm or 55nm process - actual gate length has outpaced the notional length contained in each node's title for some years. As a result, figures such as current drive, which control the performance of the core transistors, are lower than those quoted by TSMC. The NMOS transistor of Toshiba's high-speed version of the process has a current drive of 840µA/µm, around 30 per cent worse than the process that turned into TSMC's own shot at a 40nm technology.
But, if you compare with a 65nm process, where transistors often wind up in the 40nm-long range, Toshiba's numbers are par for the course. The bulk technology covered by IBM and the Common Platform partners at IEDM in 2004 shows broadly similar numbers. More importantly, the leakage in the new Toshiba process is lower than in those older processes thanks to the decision to implant nitrogen atoms in the transistor channel, the use of flash-lamp annealing and the use of high-k in the gate over the channel, without going all the way to high-k, metal-gate structures.
Among other things, these techniques cut band-to-band tunnelling, one big source of leakage in low-power transistors according to Toshiba. By putting hafnium into an otherwise conventional silicon oxynitride gate dielectric, the gate gets slightly better control over the transistor channel, improving drive current by up to 5 per cent. Toshiba takes this boost to reduce the concentration of dopant atoms in the channel. Why? They are big source of variability in deep submicron devices because you can now count the number of active dopants in a channel in the hundreds. It will not be long before you count them in tens.
The lower dopant concentration cuts the junction leakage and the variability. This gave the Toshiba engineers the confidence to scale the SRAM cell down to just 0.195µm2, a little smaller than the 0.202µm2 cell TSMC claimed on its 40/45nm process. With lower variability, there is less chance of individual cells failing, which helps keep yield high.
The contacted gate pitch for logic is also reasonably competitive with the other 40/45nm processes from the likes of IBM, Intel and TSMC, although a bit looser at 168nm versus TSMC's 162nm.
This is a process that is designed for density and low power consumption, not performance, and marks the continuing separation between semiconductor processes as feature sizes scale down. Toshiba is not alone in doing this kind of optimisation - favouring gate density over gate length - Panasonic (formerly Matsushita) has been doing the same thing. In consumer electronics, where these processes are aimed, cost is still king. That means optimising for overall die area ahead of optimising for performance. As a result, Panasonic uses longer, more conservative transistor designs.
At the fringe meeting organised by Chipworks, senior technical analyst Dick James showed pictures of recent Panasonic processes. "Panasonic is an interesting company," said James. "They bring out processes that are leading edge in terms of their [market] timing but they have far less stress and strain engineering than the competition uses. The density all comes from packing the gates closer together."
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