Seeing the shrink
The major foundries are racing ahead to get 32nm and metal gates into production.
Intel's CEO Paul Otellini calls it the 'tick tock' strategy. Every two years, the company aims to skip down to the next chipmaking process so that it can either cut the cost of making its microprocessors or put more of them onto one chip. But Intel is not alone, and the companies that build chips on contract for manufacturers without fabs are keen to do the same.
Less than a year after the first 45nm processes were put into action - for the Penryn processors at Intel and communications system-on-chips (SoCs) at TSMC - the talk is now about 32nm and beyond.
There used to be some breathing space between semiconductor processes: about three years or so. Now that time has shrunk to two years, largely because all the other tricks used to reduce the size of transistors on chips have run out of steam.
So, just months after 45nm processes started to ramp, companies are now touting the 32nm process and even its little brother, the 28nm process. And the main foundry players picked the same week at the end of September to do it. On Monday 29 September, TSMC said it would pay relatively little attention to the 32nm node and, instead, concentrate on a pair of processes tagged as 28nm. The reason was that this would provide a doubling in transistor density compared with the 40nm that the company brought on stream at the start of the year.
A day later, IBM and the other companies that make up the Common Platform alliance said they would continue to treat 32nm as a full rather than a 'half node'. However, they confirmed that a 28nm half-node version was in planning, and that it would be ready at about the same time as TSMC's own 28nm process.
TSMC's director of advanced process marketing KT Sung says the company aims to start ramping up the first of its two 28nm processes early in 2010. This would follow closely after a 32nm process that would get underway in the third quarter of 2009, about the same time as the Common Platform's plan for its 32nm offering.
TSMC is working on two forms of the 28nm process, one using high-k dielectric and metal gates (HKMG) as well as a more conventional silicon oxynitride-gate process. The move to HKMG will allow the company to compete as a foundry with IBM for microprocessor and other high clock-speed designs. Intel already has HKMG in production in its 45nm-based devices.
This is the second time that TSMC has claimed it will concentrate on a process that apparently offers finer geometries than competitors. TSMC claimed when it launched its 40nm process as a foil to competitors' 45nm offerings, that it was a 10 per cent shrink of its 45nm offering. However, the dimensions of the 40nm process were the same as those quoted in a process described at the 2007 International Electron Device Meeting that was described as 45nm. Critical dimensions, such as the contacted gate pitch, were roughly in line with those announced by Intel at the same conference for its own 45nm HKMG process.
Gary Patton, vice president of IBM Semiconductor Research, acknowledged that there are some questions over the claims being made for the latest processes and whether terms such as '28nm' are being applied consistently: "We have had some discussions among ourselves as to what is being described: is it really a 28nm or a 40nm process?"
For its 28nm process, TSMC's director of advanced process marketing, KT Sung, refuses to provide a figure for the contacted gate pitch or minimum gate lengths for either the polysilicon or HKMG variants. However, there are constraints on what gate lengths are reasonable for a given application. The SiON is aimed at portable equipment, so the emphasis is on low power consumption, particularly leakage, rather than performance. This tends to favour a longer gate: design tools will now extend the gate from the standard length to cut leakage if it the transistor does not need to switch too quickly. Typically, devices aimed at the SiON version will run at lower clock speeds than those envisaged for the HKMG version, which is aimed at graphics processors and programmable logic. The transistors in these designs need to be able to switch at higher frequencies, so will tend to have shorter gates.
IBM and the Common Platform partners are not splitting their efforts on twin processes. Instead, they believe a HKMG process can do it all - at both 32nm and 28nm - and have enlisted the help of ARM to try to get them into designs for a new generation of mobile Internet device. ARM will provide provide cell libraries and processors for the metal-gate processes.
Both the 32nm and 28nm processes will use high-k gate dielectrics and metal gates, with the option of airgap dielectrics in the metal layers to reduce capacitance in designs that need to run at high clock speeds.
Mark Ireland, the vice president in charge of Common Platform work at IBM, claims: "We started this collaboration about six months ago. We were looking at this new segment for mobile Internet devices, which is expected to outgrow PCs and laptops by 2010. What is different here is that it is not just a physical IP deal. ARM is also developing enhanced IP to leverage high-k, metal-gate processes for best performance at the lowest power.
"The key is to pursue aggressively the high-k, metal-gate properties. That is why we started much earlier with ARM, to ensure the migration is very smooth."
Tom Lantzsch, vice president of marketing for ARM's physical IP division, confirms: "What is unique about this relationship is the point in time when ARM became involved in this process. We produced a test chip earlier this year and we have now done a test chip with some ARM processor cores in it. Historically, we would have got involved much later in the process."
Unlike with TSMC, at IBM Ireland the plan is to regard 28nm as a half node - a simple shrink from designs prepared for 32nm design nodes. "The 28nm half node would follow six months after the introduction of 32nm," he claims.
Power is likely to be the battleground, with IBM and TSMC making claims and counter-claims about which offers the best performance for a given amount of energy. Sung argues that the conventional SiON process has lower gate capacitance. This is a factor in how much energy is needed to switch a gate from its off to on state. An HKMG process, as its name implies, has a higher gate capacitance. This was needed to improve the ability of the gate electrode to control current flow across the channel. As Texas Instruments chief scientist Dennis Buss observes, a CMOS transistor never really shuts off. It just goes from being on to less fully on. However, by boosting the capacitance of the gate dielectric, it is possible to create a stronger electric field in the transistor channel that resists the flow of electrons. A high-k dielectric also allows the use of a thicker insulating layer between the channel and the gate electrode. This, in turn, cuts gate leakage. This leakage is not as important as subthreshold leakage, in which carriers pass through the channel even when the device is supposedly switched off. But gate leakage contributes to power consumption all the same.
The question is whether gate capacitance makes a big difference to power consumption in the context of a circuit. Sung emphasises that TSMC's calculations come into play in "front-end dominated" designs. These are chips with comparatively few metal layers where transistors are connected to near neighbours. Here, gate capacitance does play a factor in controlling power consumption. However, as the length of metal that needs to be driven increases, then the gate capacitance becomes less important and the driving factor is the metal interconnect itself. This is one reason why IBM is providing the option of airgap dielectrics in its processes. Air reduces the capacitance between metal lines, helping to improve speed or lower active power consumption.
Patton argues that, although the capacitance of the gate insulator itself is higher, the shift to HKMG provides IBM and its partners with knobs to turn to reduce power consumption. "By going to high-k, we have much better channel control. We thought SiON was pretty risky because of the issue of short channel-length control," says Patton. Going for longer gate can help with power consumption, he explains, but it could have a knock-on effect on density. "If you can't scale the polysilicon width, the only thing that can scale is the gap between the gates. That puts a lot of pressure on the gate-to-contact distance. You need finer tolerances."
Because HKMG allows for a shorter gate, Patton claims there is a further benefit to eschewing conventional SiON processes. "We are back to traditional scaling," he claims.
Sung argues that the continued use of SiON lets designers use techniques that they have learned and understood with previous generations of submicron silicon. HKMG gives them an alternative if they need speed but SiON is good if you care about cost. However, Patton counters that the risk is of pushing SiON beyond its useful life. To get the performance out of SiON, fabs need to use increasing levels of strain, which complicates the process.
Patton claims that a single-metal HKMG process competes favourably with SiON on cost once you take factors such as strain engineering into account. IBM will offer both vanilla and strain-boosted versions of the HKMG processes. If HKMG does look to be a winner, TSMC aims to have its own form in place, although it will lag the 32nm introduction from IBM and partners such as Chartered Semiconductor Manufacturing and Samsung. The question is whether, once they get the test chips back, the fabless chipmakers think SiON has had its day or that they can push it just one more node.
A little over a year ago, IBM said it had used a self-assembling polymer to put a honeycomb of vacuum cells in the layers between metal lines on a chip. That technology will make it into production with the launch of the 32nm process that the company plans with its Common Platform partners.
IBM will offer two types of airgap dielectric in its process as an option. The lower metal layers would have the self-assembling polymer to separate them; upper layers would have airgaps defined using more conventional lithography. The lines in the upper metal layers tend to be thicker and more widely spaced. The polymer provides gaps on the order of 20nm across.
This is overkill for the more widely spaced metal lines, so the gaps in these layers can also be bigger.
The main factor that now controls how dense you can make is the contacted gate pitch: the minimum distance at which you can space the gates of transistors.
This dimension is related to the number that defines a process node, such as 45nm or 32nm, but there is no hard link. In the 1990s, the node referred to the gate length, a distance that controls how fast a transistor can switch. Chipmakers then discovered ways to thin the gate of a transistor without doing much to the gate pitch itself, so that the process name became only vaguely connected to the gate length.
However, processes for a given node tend to use similar distances. In the case of a 45nm process, the pitch is about 160nm. In principle, that drops to 110nm on a 32nm process. That gate pitch is controlled by how thin you can make the contacts that reach down to the three main parts of a CMOS transistor: the gate; the source; and the drain.
The shrinking of these distances is the main reason why Intel turned away from circular contacts and turned them into thin strips instead. The wider contacts introduce higher parasitic capacitance between adjacent transistors but the contact resistance is much lower. Because low contact resistance - defined by how much conductive polysilicon touches the transistor contacts - is so critical, chipmakers are keen not to scale these distances down too quickly and, in turn, the contacted gate pitch.
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