A test of mettle
Just six months since a group of chipmakers claimed that it had put into production the most advanced processes yet for making integrated circuits, a number of the group are already talking about the next big step: doubling the density of chips by shifting from 45nm to 32nm. If, as is so often claimed, the end of Moore's Law is in sight, nobody has told these people.
It's a symptom of the way that demand to keep doubling chip density every 24 months has put pressure on the manufacturing side of integrated electronics to keep rolling out new processes on a strict two-year cycle. Whereas there used to be other ways to get that doubling, designers are really only left now with what process advances can give them (E&T, 24 January).
It means that, not long after running the first production wafers of a 45nm process, chipmakers are now trying to drum up interest in its successor. In mid-April, IBM said it had achieved a major "performance leap" for chips in the shape of its forthcoming 32nm semiconductor process. What IBM and some of the companies in its group of chipmaking collaborators had done was produce a set of test chips and the results made them confident enough to declare the 32nm process ready for customers to start to work with. IBM will start running prototypes for customers of the companies in its Common Platform alliance in the third quarter of this year.
The implication is that the companies in the Common Platform team will have a working 32nm process in the second half of 2009. They are unlikely to be alone. Intel and TSMC have already described aspects of their 32nm processes: the Taiwanese foundry did that in some detail at the International Electron Device Meeting (IEDM) last December.
Where IBM, Intel and TSMC deviate is over how the transistors are made. IBM and Intel have decided to opt for the new technology of metal gates for their 45nm processes - although companies in the Common Platform alliance do not have access to the IBM metal-gate technology initially. IBM has kept the 45nm version to itself for use by its computer operation. Intel chose metal gates and a hafnium dielectric for its current generation of processors.
TSMC has said it will provide the options of a new metal gate, based on an undisclosed formula, and a more conventional polysilicon gate structure for its 32nm low-power process. The difference lies in expected performance.
IBM has claimed the tests performed by its team show a speed boost of 40 per cent over conventional transistors with gates made using today's polysilicon. If the improvement is that good, why not do it? The answer lies in the cost.
The problem with metal gates is that, in most processes described to date, you need two different metals for the two types of transistor used in a CMOS process. That means double the number of steps during the most expensive part of the chipmaking process. Intel worked around it by adopting a so-called gate-last process - make dummy versions of the gates and then, at the last minute, etch them out and drop the right materials down the hole. It sounds difficult but Intel claimed at IEDM that it was not much more complex than previous processes.
IBM's project manager for high-k and metal-gate technology, Mukesh Khare, told E&T that the Intel approach is likely to be more expensive than the process that the mainframe maker is putting together for the future 32nm technology that will be deployed to its Common Platform partners. "That is the biggest differentiator we have. Our partners have provided us with all this great input. The process must be the cheapest," he said. "That is why our process is gate-first. We don't put something down and then remove it."
Intel disagrees. Mark Bohr, Intel senior fellow and director of process architecture and integration, says: "Given any amount of time, I think we would have chosen the replacement-gate or gate-last process because it lets us select the metals.
At the International Electron Device Meeting (IEDM) in December 2007, Kaizad Mistry, director of logic technology integration at Intel, claimed that its gate-last process only added one mask step - needed to define which holes the metals would be deposited in - and that there was no real increase in complexity because the company had eliminated a mask step elsewhere.
That does not tell the whole story of cost. Intel has to use atomic layer deposition to put down the layers of hafnium dioxide that comprise its high-k dielectric. This type of process tends to be slow. However, according to analysis by Chipworks, Intel seems to have avoided a bottleneck in the process by placing a thin layer of hafnium dioxide on top of a strip of conventionally grown silicon dioxide. Because it places layers one by one, the cost of atomic layer deposition depends on how many you lay down. Restricting that number by keeping the high-k layer thin should help keep cost down. Using silicon dioxide as an interface layer also provides a better surface for the high-k dielectric.
"To me, it's quite elegant processing," says Dick James, senior technology analyst for Chipworks.
One thing that's missing from anything that IBM has said so far is what the developers have actually done to achieve a cheaper process than Intel's. That is not particularly unusual. Although, at the beginning of last year, Intel was only too keen to say that it was swapping out silicon dioxide in favour of a hafnium oxide for the dielectric in its metal gate stack, what was missing was the detail on which metals the world's largest chipmaker was going to use. Speculation hinged on that because the use of two different metals implies a more expensive process.
Analysis by reverse engineering specialists such as Chipworks has revealed a nod to the past - with the use of aluminium in the gates, a material used in the late 1960s before polysilicon and silicon dioxide stacks came to dominate.
What is known is that IBM is working with just one type of metal and using tweaks in the process to tune the metal's properties for the two types of transistor needed. IBM is far from alone in working on this type of scheme. Some of TSMC's partners, such as NXP Semicon-ductors, are pursuing a similar path.
John Schmitz, vice president and general manager of process technology at NXP, says: "We are striving to make low-cost CMOS flows and so we are looking to a single-metal process."
The problem with metal gates is that the work function of the material that sits on top of the gate becomes vitally important. If the work function is not tuned well, the gate will not perform well. The work function differs for n- and p-channel transistors, so you need different metals. Or, as an increasing number of researchers believe, you can tune the work function of a single metal for each type of gate by using interface layers.
NXP, working with IMEC, found that a layer of dysprosium oxide on top of silicon oxynitride not only acted as a high-k dielectric but allowed the work function to be tuned for either n- or p-channel gates with the same metal stack on top.
IBM seems to be pursuing a similar approach, possibly with different materials, such as ytterbium and ytttrium, which have similar properties to dysprosium. Khare claims: "It is one metal for both NMOS and PMOS. You have to do a little bit of tuning: adjust the work function by some form of doping. But it is an adjustment not a change in the metal."
Casper Juffermans, head of the CMOS module integration department at NXP, says of its material: "The material was already known to produce a good PMOS. But the capping layer really showed a big shift for NMOS. It has two big effects: work-function tuning and, the surprising finding, it is two or three orders of magnitude better than hafnium silicide."
However, cost remains an issue. Juffermans adds: "Dysprosium is an exotic metal." The aim is to develop the process far enough that NXP's main foundry TSMC will want to use it. "We have to find more data. I have the impression that if TSMC can find a way to not use high-k metal gates, they will go for it, at least at 32nm. But high-k metal gates do offer performance benefits."
At IEDM, CC Wu admitted that the performance of p-channel gates, in particular, with polysilicon gates depends very strongly on design. The problem is that, since the 90nm process, fabs have applied strained-silicon techniques to boost the speed of transistors.
Unfortunately, as transistors get smaller, the effect of a given level of strain reduces and the process engineers have to put higher levels of strain in, which can lead to defects. The problem is particularly acute for p-channel transistors, which use an embedded layer of silicon germanium to apply the strain. The total amount of strain depends on how large the effective volume of silicon germanium is and that depends on the spacing between polysilicon gates.
The result, said Wu, is: "You need careful design to maximise circuit performance, but that affects circuit density."
Both Khare and Bohr claim the shift to metal gates removes this problem. "There is a big performance advantage for PMOS through the replacement-gate process. Anyone who questions the replacement gate process should be silenced by that finding."
The effect on device performance at 32nm could be even more marked as the transistors need to be even more tightly packed. What IBM has disclosed about its 32nm process bears out this prediction.
IBM and its partners expect to be able to deliver a process that exceeds the industry consensus on what is needed at the 32nm node. The consensus is summed up in the pile of documents that go by the name of the International Technology Roadmap for Semiconductors (ITRS). Taken together, the documents are effectively the guidelines for what the industry needs to stay on Moore's Law.
Scattered throughout the PDFs are tables of specifications that semiconductors should get close to if they are to be useful at a given process geometry. The numbers are all colour coded: yellow means tricky but possible; red means nobody has an answer yet, or at least one they've shared in public.
As Intel more or less controls the high-end microprocessor space, the main battleground is in what the ITRS terms the low operating power (LOP) and low standby power (LSTP) processes. There is a question mark over how long LSTP can stay in business. Today, transistors are leaky things, and current just dribbles out of them even when they are supposed to be off. The ITRS has upped what it considers acceptable leakage to 30pA/µm. No one is quoting anywhere near that number.
Both IBM and TSMC's processes seem to aimed squarely at the LOP zone. Based on what TSMC's deputy director of low-power technology Shien-Yang Wu said at IEDM, the polysilicon-gate version looks more or less on track in ITRS terms with a current drive of 700µA/µm against a leakage current of 1nA for an NMOS transistor. Current drive (Ion) is one of the figures of merit that process engineers use to work out whether a transistor is going to be good enough. The ITRS quotes 760µA/µm for the 2009 timeframe.
IBM's alliance, with their metal-gate stack, look to be in better shape with a figure 1000µA/µm against 1nA/µm. The metal-gate option has given IBM, Chartered Semiconductor Manufacturing and others in the alliance some latitude to cut leakage and maybe get the process into the LSTP zone as well, as current drive tends to scale down with off-current. That does not seem to be something that TSMC will be able to do if it sticks with the current plans for a 32nm process that uses a more conventional polysilicon gate structure.
The decision between foundries is likely to come down to a cost-performance trade-off. It is possible that IBM has come up with a metal-gate process that is comparable in cost to that of a polysilicon gate. However, it may be that IBM aims to sell on performance versus absolute cost.
Looking at 32nm as a foundry process, the Common Platform process may be forced into the upper end of the LOP niche against TSMC, which holds the lion's share of the foundry business already, holding on with what is likely to be a cheaper process at the low end, with a metal gate for high-performance designs. To get performance with the polysilicon version, users may have to sacrifice density. However, raw clock speed is nowhere near as important as raw density in many foundry-destined designs.
What is clear is that there is no let up in the pace of process development. With early prototyping shuttles beginning later this year, it seems likely that the 32nm process, from a number of sources, will be running by late 2009, two years after 45nm appeared.
Geometry wars - the disappearing node
According to Kevin Gibb, an analyst at Chipworks, traditional notions of what determines a process node have gone out of the window. The number quoted generally refers to the length of the transistor gate, but this is far from a reliable measurement. Writing on the company's blog, Gibb claims the gates on Matsushita's 45nm process are similar to those of other companies' 90nm processes. However, this should not come as too much of a surprise.
The Matsushita parts were destined for cheap DVD players that cost less than $50. Density is everything on these parts as it's the ability to pack almost all the electronics onto one chip that allows complex devices to ship for such prices. High clock speed is not an issue in these parts. In that environment, shortening the gate simply increases the power consumption. This is because, as the length of the gate reduces, so does the threshold voltage - the voltage at switch the device switches from off to on. As that threshold voltage comes down, the amount of current that continues to pass through a transistor that is supposedly off - the so-called subthreshold leakage - increases.
However, the best way to improve transistor switching speeds is to lower the threshold and, therefore, use a shorter gate. Intel's Presler had to be able to run at multi-gigahertz clock rates, so the designers would naturally favour a gate that is considerably shorter than that used by Matsushita.
An optimisation that designers are using to cut leakage power wherever possible is to slightly increase the gate length on logic paths that do not need high performance.
However, these alterations to gate length do not greatly affect the density of a chip. "Contacted gate pitch is perhaps the most important [design] rule for density," says Kaizad Mistry, director of logic technology integration at Intel.
Gibb argues that contacted gate pitch is the best predictor of a node. There is a good reason for that: it is the one dimension that ties directly into device density as it directly governs how tightly you can pack real logic circuits and memory cells. There is another reason why gate length is becoming problematic.
In the late 1990s, gate lengths reduced dramatically as techniques such as optical proximity correction and phase-shift masking came to the fore. It suddenly became possible to make much shorter gates than were possible before and the industry, chasing clock speeds, chose to scale gate length much faster than Moore's Law. Now, power consumption dominates the equation, so gate length reductions have slowed dramatically.
On a typical 65nm process, the gate length would be expected to be around 40nm - which is why Gibb regards Matsushita's 55nm measurement to be more redolent of a 90nm process. However, by the time we hit 45nm, the gate length has barely moved. Even Intel is on a gate with a working length of around 35nm, according to Chipworks' measurements and Intel's own claims. The effective length of a gate is a little lower than its drawn length, so there was hardly any scaling in that dimension from 65nm to 45nm. Intel took most of the performance gains from its changes to the way the gate is made.
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