Into the fast lane
At the recent International Electron Device Meeting in December last year, TSMC took the wraps off its plans for the 32nm process: the next step after the 45nm technology, which itself only started production in the autumn. Normally at this conference, and particularly given a talk about the plans for a process, all of the attention focuses on digital performance. How small are the transistors? How much SRAM can you squeeze into a square millimetre?
This time it was different. There was talk about the 2Mb SRAM test chip and how the company had managed to shrink the memory cell further. But TSMC's deputy director of low-power technology, Shien-Yang Wu, wanted to talk much more about how the process would support analogue circuitry, focusing on the flicker noise problem and how strained silicon has made it worse over time and how the company redesigned the core transistors to improve properties such as transconductance.
Historically, only the very brave or foolhardy would seek to put complex analogue circuits onto a brand new process. Companies would tend to move to the most advanced process node they could afford with their digital parts, aiming to take advantage of smaller SRAM cells and logic gates. But, with analogue circuitry, they have been more circumspect: choosing to stick with older technologies. The 0.35µm process can support circuits that need to operate at 5V. The 0.18µm process remains popular among analogue designers because it is now mature and stable and can be tweaked to support the higher voltages that engineers prefer to work with if they can.
It and the 0.15µm 'half node' still account for more than a quarter of TSMC's revenues, and earn almost twice as much as all the older nodes put together – and almost three times as much as the two-year-old 65nm process. And the foundry is still ramping up capacity. The equipment from Atmel's Tyneside fab in the UK is being moved into a new fab in China to handle demand for the 0.18µm process.
The bad news
There are other reasons for not pursuing Moore's Law when it comes to analogue circuitry. The only thing that works in favour of smaller transistor geometries is speed. The cutoff frequency of TSMC's 32nm transistor stands at 270GHz. The cutoff frequency for a conventional 0.18µm process is closer to 60GHz.
The list of problems is a lot longer. Rather than getting smaller, some circuit elements get bigger and a lot just have to stay the same.
Bob Tait, marketing director of mixed-signal design specialists S3, said: "The digital domain scales very nicely in accordance with Moore's Law. But that is not the case for analogue technology."
Given the same materials, an inductor's performance, for example, depends on its size. Scaling it just makes for a poorer-fitting inductor.
All that happens, said Rafi Nave, vice president and chief technology officer of Israeli foundry Tower Semiconductor, is: "You pay for the higher cost of the mask set and you don't get the benefit of the smaller chip area."
The increase in size comes from the way that analogue engineers have to deal with the shrinking voltages that each successive process technology imposes. There are plenty of topologies that circuit designers have developed over the years to cope with low voltages. However, they were often consigned to the shelf because the circuits needed to be bigger than the tried and tested alternatives. Now, engineers are going back to those old conference papers, dusting them down and putting the ideas into practice on the latest process technologies.
Why? Because it cuts costs if you are working in very high-volume markets, such as chips for mobile phones and other consumer products. Former president of TSMC in Europe Kees den Otter said: "The volumes dictate where and when you will go. You can see the economies of scale at work for the one that is most advanced."
Navraj Nandra, director of product marketing for mixed-signal IP at Synopsys, said: "A lot of our customers are pushing process technology."
Putting high-quality analogue onto the same substrate as millions of gates of digital logic is not for the faint-hearted. The logic transistors switch practically in unison, which forces high-frequency noise into the silicon die and the on-chip wiring. However, the noise is difficult to model.
Sergio Kusevitsky, vice president of the Chipidea analogue group at MIPS Technologies, said: "There is no simulation for substrate noise. We never know what will happen. There are a lot of things to be done in the EDA world."On top of that, issues giving digital designers headaches are potentially even worse for the analogue engineer. For example, statistical variability is getting worse with each reduction in transistor size.
Professor Asen Asenov of the University of Glasgow explained that small, atomic-level variations in how the transistors are made means that each one ends up slightly different: "The shape of the device becomes unique. In some regions, a reduction of the width of the transistor channel happens. And there will be other cases where it increases. That causes variation in the current. You can predict the average shape of the device, but you can't say what the precise shape of each transistor will be."
A second source of variability is the position of dopant atoms in the transistor channel. "They are very heavily doped channels," said Nandra, who noted that this type of doping is good for digital but very painful for analogue engineers. Small changes in the location of the dopant atoms can lead to big differences in transistor behaviour from an analogue point of view.
Marcel Pelgrom, head of mixed-signal research at NXP Semiconductors, said it was the 90nm process where statistical variation started to take over. It means that classical techniques used to deal with variation no longer work. "Differential design eliminates global variation. But, with these statistical effects, circuits remain sensitive to local variations," he said.
There is some good news. There is less of a penalty to moving to a process that has not matured, whereas that used to be a very courageous decision for a design team with older processes. An immature process was one where you had little idea of how it was going to behave from week to week. Those changes are manageable in digital circuitry; tough to address in analogue without a lot of area-intensive techniques to compensate for the anticipated alterations.
"Usually, when you ramp up a process, you improve the control over it," said Asenov. With statistical local variability that is no longer the case: it is always there. So, it needs to be designed out and it makes little different when you start.
One technique is to analyse the behaviour of the analogue circuits and correct for them digitally. This was one approach tried by NXP in an analogue-to-digital converter (ADC) that had to cope with noise from a charge-coupled device image sensor. Although the analogue converters themselves were not that good, the correction provided good overall accuracy.
Jon Hudson, senior vice president and general manager of CSR's PC, automotive and consumer business units, claimed the ability to tune dynamically is important in modern radio-frequency designs. Having started on fairly old processes, the push for integration has led to CSR working on more aggressive processes. "One thing that CSR has done always is to have more software control over how the RF operates. Those same techniques allow us to live with more uncertainty in the process."
"By chosing a suitable analogue topology, you can tune out the error. It is done today in IQ demodulators in radio and in sigma-delta converters," claimed Pelgrom. "However, there are limits to these techniques in ADCs as the major issue today is jitter."
Issues such as mismatch can be corrected using digital analysis. Jitter is much tougher and is exacerbated by the way that transistors with subtly different dimensions will switch at different rates. "It is the real killer," claimed Pelgrom.
"We have seen digital circuit techniques being applied to compensate for the fact that the analogue designs can't reach the performance required," said Tait. "And customers are using more statistical approaches. They are taking a more pragmatic view of what is likely to happen and that has been factored in."
The trend towards higher variability is not necessarily one-way. Jean-Luc Pelloie, director of silicon-on-insulator technology at ARM and manager of the company's Grenoble design centre, said: "I think there will be a change in the coming nodes. One of the major changes will be the switch to metal gates from polysilicon. Variability related to dopant fluctuations will be reduced: with a metal gate you need less doping in the channel. This will provide a major advantage for switching to new materials.
"Gate leakage is also a problem for analogue as leakage is a contributor to noise sources," Pelloie added. Metal gates with high-k dielectrics cut gate leakage as much as tenfold by allowing thicker insulating layers between the transistor channel and the metal gate itself.
Need for margin
Variability is an issue that the intellectual-property suppliers have had to face with older processes, as they need to have circuits that can work across a range of designs and processes. Joachim Kunkel, vice president and general manager of the IP division at Synopsys, said: "On the analogue and mixed-signal side, functionality is not a problem. The problem is getting the design to be robust enough, getting more and more margin into the design."
Nandra said: "Analogue designers should be skilled enough to work around problems. The process technology will do what it has to do. The days are long gone when designers can go to a fab and say 'I want a more accurate polysilicon module to do double-layer poly'."
The foundries have worked to improve their support for mixed-signal design, said Nandra. The simulation models that the foundries now provide have become very accurate, he said. The result is that we now have an industry gearing up to move analogue design into the fast lane, having decided that the cost benefits in high volume outweigh the risks of playing safe with older technologies.
The trend to do more at the advanced processes has put new demands on engineers.
"The skill sets have changed from ten years ago. Then, you could use people of [National Semiconductor engineer] Bob Pease's generation to design. Those skill sets are a little bit redundant at deep submicron geometries," said Navraj Nandra of Synopsys. "There is a need for people who understand process technology and who understand the applications space."
Sergio Kusevitsky of MIPS Technologies added: "For 20 years, designers have followed the rules learnt in university. For the first time, there is a feeling that these rules may break in the near future."
Designers have to think differently about how to get a result. "You have to meet 5V tolerance using a 1.8V transistor," said Nandra. "And you need circuit innovation in order to get analogue precision on a digital technology. The technologies are getting more complex. If you look at the performance of the metal lines between 90nm and 45nm, you see a four- to five-fold increase in rho [resistivity]. You are getting larger RC [resistance and capacitance-induced] delays.
"There is some good news - we are seeing more alignment of process technologies," Nandra added.
Transistor-level tweaking by the circuit designer will become more common - not in the process parameters but in how the devices are laid out. "People will be removing transistors from the vertical stack and making them more horizonal to meet power supply rejection-ratio requirements," Nandra claimed, noting that some things will seem like a return to earlier days. "And the direction of the polysilicon will affect how you place the IP cores on the chip. It is like going back to the gate array, where you talk about north, south, east and west when placing elements."
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