A lot of people are worried about silicon scaling giving up the ghost as we move to 20nm - the process that is just beginning to move into production - and beyond. The way things seem to be going, we may run out of nanometres before Moore's Law runs into a brick wall. But that's not necessarily thanks to technical advances but the chip industry's use of grade inflation.

The leading foundries are preparing processes that carry names like 14nm and 16nm but which are, in terms of scaling, not all that different from their existing 20nm offerings. Instead, they are using their own introduction of finFETs, similar to the trigate transistors used by Intel at 22nm, to justify the change in size.

The gamesmanship on process names goes back to the 45nm generation when Intel threw a curveball by introducing a high-k metal-gate process that, under the hood, used some new design techniques to maximise density. The industry has yet to catch up with the 'one-dimensional' design style Intel now uses, which was introduced to make it possible to use novel lithographic techniques such as double patterning. The resulting Penryn-generation processors turned out to be surprisingly small.

Intel tends to use the contacted gate pitch as its key metric for determining how effective scaling is. For the most part, this pitch scales at 0.7x per generation -  which approximates to a two-fold increase in areal density each time. Companies can and do quote other metrics but this is arguably the best indicator of true logic density given that you can't do much with transistors unless you connect them to each other, and that involves making room for the contacts that join the gate electrodes to the rest of the wiring.

A closer look at Intel's graph shows that the company did a little better than that for the generations up to 65nm and then starting coming off the pace for 45nm, 32nm and 22nm. Although 45nm was more aggressively scaled than competitors expected, it still resulted in a smaller change to contacted gate pitch than that found with the two or three prior processes. The pace has slackened further since then. But if you draw the blobs on the graph big enough, the company is still more or less on the line even at 22nm. And it's not as if the competition are doing a whole lot better.

When first introduced, the 45nm processes from competitors showed less aggressive scaling from 65nm. So the idea of jumping straight to the 'half node' of 40nm was born. This turned out to have more or less the same contacted gate pitch as Intel's 45nm. It was just that 40nm sounded better.

The situation did not reset for the 32nm generation. The foundries introduced 28nm processes that were more or less in the same ballpark as Intel's 32nm and this has continued down to 22nm/20nm. The 14nm and 16nm processes stretch the measurement differential a little bit further. How far depends on the metric you use.

For example, GlobalFoundries' 14XM process puts a finFET on its existing 20nm platform. The transistor itself is smaller, which is how the foundry justifies the change, pointing out that the contacted gate pitch number has not had any connection to process name for years - it's usually in the range of 2.5x the process node's nominal dimensions. The argument for using the smaller number is that Intel has fallen off the scaling curve for gate length quite badly.

For about a decade, gate lengths were less than the process' nominal dimension. Then things slowed down dramatically. Intel took advantage of the move to finFET, and its better properties, at 22nm to relax gate-length scaling to the point that its effective length is some 30nm. In contrast, Samsung's 20nm process name matches the actual gate length. GlobalFoundries claims it will be more aggressive for its '14nm' process although we don't yet know whether the gate length will be close to the name. As the process is optimised for low power - and short gates are bad for energy consumption - it seems likely that GlobalFoundries, as well as TSMC on its '16nm' process, will err in the same direction as Intel.

The issue for the foundries is that even despite an apparent speed-up in the time to get to nominally sub-20nm processes, effective scaling will be slower. And, with that, the reductions in cost will be far less. The payoff is that, with a move to finFETs, power consumption should be significantly better, which may be enough to justify migration for a number of customers. The question is whether the industry will attempt to pull off something similar for 10nm to try to stay nominally on Moore's Law or retrench and take maybe three or four years after the '14/16nm' generation to get back on the curve of 2x-per-generation in terms of area scaling.