At the International Electron Device Meeting (IEDM) in Washington DC this week, senior Intel engineer Mark Bohr gave his prognosis for the future of the silicon transistor  - and what might follow it. Overall, the forecast was light on surprises: Bohr seems to hold similar views to others working on future devices.

Intel remains bullish on the use of III-V materials - the company has been working with Qinetiq for a number of years now on quantum-well transistors that lay a lattice of indium gallium arsenide on top of a silicon wafer. This is not easy: the number of buffer layers needed always makes me think of the fairy tale of the Princess and the Pea. And Bohr recognises that there are still formidable challenges in making these devices viable. Other researchers, such as those as MIT, reckon that although these transistors might offer formidable speed at low power on paper, they might not turn out to be so good in reality.

So, in common with researchers at IBM and MIT, Bohr reckons that the silicon nanowire has potential. But, he points out that these may well fall foul of the same problems faced by III-V: high resistance getting carriers in and out of the transistor itself. Making very thin vertical nanowires uniformly is also a formidable challenge in the fab.

Then there are the exotic spin-based and quantum-effect devices that might follow on from the nanowire transistors. But, as Bohr says, all of these have issues when it comes to integration: "A likely outcome is that some of these exotic solutions will emerge as successful replacements for silicon MOSFETs, but only in narrow applications."

It is possible to see spin-based devices being used for memory applications but they may prove to be unsuitable for interfacing with the real world through analogue circuits. The unmentioned future in Bohr's analysis is what will make it possible to put various types of transistor together. Monolithic integration will probably be too expensive. Bohr's colleague Shekhar Borkar has been promoting the probable answer for close to a decade: 3D integration. We will see CMOS being used as the interface to the processors and memory sitting in a stack, but they themselves will be separated into CMOS, quantum and nanotechnology-based circuits each tuned for a specific function.