We are looking for an electrical engineer with around 4- 6 years of design experience to join and work with an able and talented group of engineers..
- Recruiter: Max Fordham LLP
- England, Cumbria, Barrow-In-Furness
- Competitive package
As an Engineering Manager - Naval Architecture you will be managing the Whole Boat Architecture and Concepts team tasked with supporting the delivery of the remaining Astute submarines, and developing new technology for future submarine programmes.
- Recruiter: BAE Systems
- Bootle, Cheltenham and London
- Competitive + Benefits
With expertise and influence, you’ll set the standard for nuclear safety.
- Recruiter: Office for Nuclear Regulation
- Albany or Palmerston North
This role offers an outstanding opportunity to lead and further develop a well-established and internationally recognized School.
- Recruiter: Massey University
- City of Westminster, London (Greater)
- Circa £65,000 (There may be more for an exceptional candidate)
You will lead on a number of engineering infrastructure and associated workstreams under direction from the Deputy Director
- Recruiter: House of Commons
- Zurich, Canton of Zürich (CH)
The successful candidate is expected to develop a strong and visible research programme in the area of control and diagnostics of building systems
- Recruiter: ETH Zurich
- England, Warwickshire
- £25000 - £28000 per annum
Profile: To provide a range of support activities to the Construction delivery teams to ensure the effective delivery, document management, reporting and closure of projects. To support the Senior Project Manager in the measurement of function performance
- Recruiter: National Grid
- South West England
Exciting opportunities have arisen within as we expand to meet the growing demands of the UK Submarine Programme.
- Recruiter: Babcock
- Humber Refinery, South Killingholme, North Lincolnshire DN40 3DW
- £60k - 75k plus extensive Compensation and benefits package, dependent upon experience
Experienced Process Control Leader providing leadership and technical support for Oil Refinery. Extensive Compensation and benefits package.
- Recruiter: Phillips 66
- Warwick, Warwickshire
You will be required to lead the regional Customer Services strategy and resources to maximise Customer satisfaction.
- Recruiter: Siemens
8 December 2011 by Chris Edwards
Intel remains bullish on the use of III-V materials - the company has been working with Qinetiq for a number of years now on quantum-well transistors that lay a lattice of indium gallium arsenide on top of a silicon wafer. This is not easy: the number of buffer layers needed always makes me think of the fairy tale of the Princess and the Pea. And Bohr recognises that there are still formidable challenges in making these devices viable. Other researchers, such as those as MIT, reckon that although these transistors might offer formidable speed at low power on paper, they might not turn out to be so good in reality.
So, in common with researchers at IBM and MIT, Bohr reckons that the silicon nanowire has potential. But, he points out that these may well fall foul of the same problems faced by III-V: high resistance getting carriers in and out of the transistor itself. Making very thin vertical nanowires uniformly is also a formidable challenge in the fab.
Then there are the exotic spin-based and quantum-effect devices that might follow on from the nanowire transistors. But, as Bohr says, all of these have issues when it comes to integration: "A likely outcome is that some of these exotic solutions will emerge as successful replacements for silicon MOSFETs, but only in narrow applications."
It is possible to see spin-based devices being used for memory applications but they may prove to be unsuitable for interfacing with the real world through analogue circuits. The unmentioned future in Bohr's analysis is what will make it possible to put various types of transistor together. Monolithic integration will probably be too expensive. Bohr's colleague Shekhar Borkar has been promoting the probable answer for close to a decade: 3D integration. We will see CMOS being used as the interface to the processors and memory sitting in a stack, but they themselves will be separated into CMOS, quantum and nanotechnology-based circuits each tuned for a specific function.
Posted By: Chris Edwards @ 08 December 2011 12:15 PM General
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